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| FUJITSU SEMICONDUCTOR DATA SHEET DS06-20210-2E Semicustom CMOS Standard Cell CS101 Series DESCRIPTION CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user's demands for lower power consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three types of core transistors with a different threshold voltage can be mixed according to user application. The design rules match industry standards, and a wide range of IP macros are available for use. As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the highspeed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps. FEATURES * Technology : 90 nm Si gate CMOS 7- to 10-metal layers. Low-K (low permittivity) material is used for all dielectric inter-layers. Three different types of core transistors (low leak, standard, and high speed) can be used on the same chip. The design rules comply with industry standard processes. Power supply voltage : +1.2 V 0.1 V (standard) Operation junction temperature : - 40 C to + 125 C (standard) Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1) Gate power consumption : Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1) High level of integration : Up to 91 million gates Reduced chip sized realized by I/O with pad. Support for a wide range of cell sets (from low power versions to ultra high speed versions). Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incorporated. Compiled cell (RAM, ROM, others) Support for ultra high speed (up to 10 Gbps) interface macros. Special interfaces (LVDS, SSTL2, etc.) Supports use of industry standard libraries (.LIB). Uses industry standard tools and supports the optimum tools for the application. (Continued) * * * * * * * * * * * * * CS101 Series (Continued) * Short-term development using a physical prototyping tool * One pass design using a physical synthesis tool * Hierarchical design environment for supporting large-scale circuits * Support for Signal Integrity, EMI noise reduction * Support for static timing sign-off * Optimum package range : FBGA, FC-BGA, PBGA,TEBGA MACRO LIBRARIES (including those in preparation) 1. Logic cells (about 400 types) Library sets having three different types of core transistors with a different threshold value are provided. * Adder * AND * AND-OR * AND-OR Inverter * Buffer * Clock Buffer * Decoder * Delay Buffer * ENOR * EOR * Inverter * Latch * NAND * NOR * OR * OR-AND * OR-AND Inverter * SCAN Flip flop * Non-SCAN Flip Flop * Selector * Others 2. IP macros Compliance with the design rules recommended by the industry standard STARC (Semiconductor Technology Academic Research Center) recommendations which means a wide range of commercially available IP macros can be used. Fujitsu plans to offer the following macros. ARM9 CPU/DSP DSPs for communications, AV, and similar applications, others Multi-media processing macro JPEG, MPEG, others Mixed signal macro Compiled macro PLL ADC, DAC, OPAMP, others RAM (1-port, 2-port), ROM, product sum calculator, others Analog PLL 3. Special I/O interface macro Interface macro Fast I/F macro LVDS, SSTL2, HSTL, GTL, others 6 Gbps I/F, 10 Gbps I/F, others 2 CS101 Series COMPILED CELL Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS101 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.) 1. Clock synchronous single-port RAM (1 address : 1 read/write) Column type 4 8 16 Memory capacity (bit) 16 to 144 K 32 to 576 K 64 to 576 K Word range (word) 16 to 1 K 32 to 8 K 64 to 16 K Bit range (bit) 1 to 144 1 to 72 1 to 36 2. Clock synchronous dual port RAM (2 address : 2 read/write) Column type (bit) 4 16 Memory capacity (bit) 16 to 144 K 64 to 144 K Word range (word) 8 to 1 K 32 to 4 K Bit range (bit) 2 to 144 2 to 36 3. Clock synchronous ROM Column type 16 64 Memory capacity (bit) 256 to 4 M 1 K to 4 M Word range (word) 128 to 16 K 512 to 64 K Bit range (bit) 2 to 256 2 to 64 4. Clock synchronous register file (2 address : 1 read, 1 write) Column type 1 Memory capacity (bit) 8 to 18 K Word range (word) 4 to 128 Bit range (bit) 2 to 144 5. Clock synchronous register file (4 address : 2 read, 2 write) Column type 1 Memory capacity (bit) 8 to 18 K Word range (word) 4 to 128 Bit range (bit) 2 to 144 LARGE CAPACITY MEMORY Clock synchronous single-port RAM (1 address : 1 read/write) Column type Memory capacity (bit) Word range (word) 16 64 K to 9 M 8 K to 64 K Bit range (bit) 8 to 144 3 CS101 Series ABSOLUTE MAXIMUM RATINGS Rating Min - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 55 - 40 Max + 1.8 + 3.6 + 4.6 VDDI + 0.5 ( 1.8) VDDE + 0.5 ( 3.6) VDDE + 0.5 ( 4.6) VDDI + 0.5 ( 1.8) VDDE + 0.5 ( 3.6) VDDE + 0.5 ( 4.6) + 125 + 125 *4 *4 Parameter Symbol Application VDDI (Internal) Unit V V V V V V V V V C C mA mA Power supply voltage VDD VDDE (External 2.5 V) VDDE (External 3.3 V) 1.2 V Input voltage *1 VI 2.5 V 3.3 V 1.2 V Output voltage Storage temperature Operation junction temperature Power supply pin current *2 Output current *3 VO Tstg Tj ID IO 2.5 V 3.3 V Plastic package per VDD, VDDI, VDDE VSS pin *1 : The values vary depending on the type of macros. *2 : Maximum power supply current that can steadily flow. *3 : Maximum output current that can steadily flow. *4 : Contact your Fujitsu representative for details. Note : VSS = 0 V WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 4 CS101 Series RECOMMENDED OPERATING CONDITIONS * Single power supply (VDD = 1.2 V 0.1 V) Value Min 1.1 VDD x 0.7 - 0.3 - 40 Typ 1.2 Max 1.3 VDD + 0.3 VDD x 0.3 + 125 (VSS = 0 V) Unit V V V C (VSS = 0 V) Value Min 2.3 1.1 1.7 VDDI x 0.7 - 0.3 - 0.3 - 40 Typ 2.5 1.2 Max 2.7 1.3 VDDE + 0.3 VDDI + 0.3 + 0.7 VDDI x 0.3 + 125 Unit V V V V V V C (VSS = 0 V) Value Min 3.0 1.1 2.0 VDDI x 0.7 - 0.3 - 0.3 - 40 Typ 3.3 1.2 Max 3.6 1.3 VDDE + 0.3 VDDI + 0.3 + 0.8 VDDI x 0.3 + 125 Unit V V V V V V C Parameter Power supply voltage H level input voltage L level input voltage Operation junction temperature Symbol VDD VIH VIL Tj * Dual power supply (VDDE = 2.5 V 0.2 V, VDDI = 1.2 V 0.1 V) Parameter Power supply voltage H level input voltage L level input voltage 2.5 V 1.2 V 2.5 V CMOS level 1.2 V CMOS level 2.5 V CMOS level 1.2 V CMOS level Symbol VDDE VDDI VIH VIL Tj Operation junction temperature * Dual power supply (VDDE = 3.3 V 0.3 V, VDDI = 1.2 V 0.1 V) Parameter Power supply voltage H level input voltage L level input voltage 3.3 V 1.2 V 3.3 V CMOS level 1.2 V CMOS level 3.3 V CMOS level 1.2 V CMOS level Symbol VDDE VDDI VIH VIL Tj Operation junction temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 CS101 Series ELECTRICAL CHARACTERISTICS * Single power supply : VDD = 1.2 V (VDD = 1.2 V 0.1 V, VSS = 0 V, Tj = - 40 C to +125 C) Conditions IOH = - 100 A IOL = 100 A VIL = 0 at pull-up VIH = VDD at pull-down Value Min VDD - 0.1 0 Typ 12 (Target value) Parameter H level output voltage L level output voltage Input leakage current Pull-up/Pull-down resistor Symbol VOH VOL IL RP Max VDD 0.1 Unit V V A k * Dual power supply : VDDE = 2.5 V, VDDI = 1.2 V (VDDE = 2.5 V 0.2 V, VDDI = 1.2 V 0.1 V, VSS = 0 V, Tj = - 40 C to + 125 C) Parameter H level output voltage L level output voltage Input leakage current Symbol VOH3 VOH2 VOL3 VOL2 IL Conditions Value Min Typ 25 Max VDDE VDDI 0.2 0.1 Unit V V V V A k 2.5 V output, IOH = - 100 A VDDE - 0.2 1.2 V output, IOH = - 100 A VDDI - 0.1 2.5 V output, IOL = 100 A 1.2 V output, IOL = 100 A 2.5 V, VIL = 0 at pull-up/ VIH = VDDE at pull-down 1.2 V, VIL = 0 at pull-up/ VIH = VDDI at pull-down 0 0 pull-up/Pull-down resistor RP 12 k * Dual power supply : VDDE = 3.3 V, VDDI = 1.2 V (VDDE = 3.3 V 0.3 V, VDDI = 1.2 V 0.1 V, VSS = 0 V, Tj = - 40 C to + 125 C) Parameter H level output voltage L level output voltage Input leakage current* Symbol VOH3 VOH2 VOL3 VOL2 IL Conditions 3.3 V, IOH = - 100 A 1.2 V, IOH = - 100 A 3.3 V, IOL = 100 A 1.2 V, IOL = 100 A 3.3 V, VIL = 0 at pull-up/ VIH = VDDE at pull-down 1.2 V, VIL = 0 at pull-up/ VIH = VDDE at pull-down Value Min VDDE - 0.2 VDDI - 0.1 0 0 15 Typ 33 Max VDDE VDDI 0.2 0.1 4 70 Unit V V V V A k pull-up/Pull-down resistor RP 12 k * : The input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor is used. 6 CS101 Series AC Characteristics (with low power consumption, high density CS101SL library used) Parameter Delay time Symbol tpd *1 Value Min typ *2 x tmin *3 Typ typ *2 x ttyp *3 Max typ *2 x tmax *3 Unit ns *1 : Delay time = propagation delay time, enable time, disable time *2 : "typ" is calculated based on the cell specifications. *3 : Measurement condition Measurement condition VDD = 1.2 V 0.1 V, VSS = 0 V, Tj = - 40 C to +125 C tmin 0.62 ttyp 1.00 tmax 1.57 I/O Pin Capacitance Parameter Input pin Output pin I/O pin Symbol CIN COUT CI/O Value Max16 Max16 Max16 Unit pF pF pF Note : The capacitance values vary depending on the package and pin positions. DESIGN METHODS Fujitsu's Reference Design Flow provides the following functions that help shorten the development time of large scale and high quality LSIs. * High reliability design estimation in the early stage of physical design realized by physical prototyping. * Layout synthesis with optimized timing realized by physical synthesis tools. * High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and crosstalk. * I/O design environment (power line design, assignment and selection of I/Os, package selection) considering noise. PACKAGES Packages available for existing series can be used for CS101 series. This allows smooth replacement with previously developed products. Please contact your Fujitsu agent for details of delivery times. FBGA package PBGA package TEBGA package : Max 424 pins : Max 420 pins : Max 900 pins FC-BGA package : Max 2116 pins (Packages under planning are included.) 7 CS101 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0602 (c) 2006 FUJITSU LIMITED Printed in Japan |
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